The present invention relates to a multiprocessor system of a computer, and more particularly to control method and apparatus suitable for constructing a virtual machine on a multiprocessor system.
In a conventional multiprocessor system such as System 370 of International Business Machines Corporation, when one of processors of the multiprocessor system executes an instruction which requires signaling of the processor, the signaling is effected to all processors of the system to synchronize the execution. Such instructions include a purge translation buffer extended (PTLBE) instruction, an invalidate page table entry (IPTE) instruction, a set storage key extended (SSKE) instruction, and a reset reference bit extended (RRBE) instruction.
The PTLBE instruction is an instruction for a multiprocessor system and it requests to all processors of the system to invalidate all entries in the address translation look-aside buffer which have been valid so far. Accordingly, when the PTLBE instruction is issued, the processor which has issued that instruction invalidates the address translation look-aside buffer of its own and signals to all other processors to invalidate their address translation look-aside buffers. The other processors of the system respond to the signal to invalidate the address translation look-aside buffers of their own. The invalidating processes are effected in synchronism in the system, and when the invalidation of the address translation look-aside buffers of all processors has been completed, an instruction next to the signaling instruction is executed.
The IPTE instruction is an instruction used when a correspondence relationship between a real page in a real memory and a virtual page in a virtual memory no longer exists because of page-out processing. This instruction sets an invalid bit (I bit) of an entry of a page table to be invalidated to "1". Since the page to be invalidated may have already been registered in the address translation table, the content of the address translation look-aside buffer is checked, and the entry of the address translation look-aside buffer whose page field and page table start address used to register the entry of the address translation look-aside buffer are identical to a page field and a page table start address designated by the IPTE instruction and which is identical to the content of the page table entry designated by the IPTE instruction is invalidated. If the system is of multiprocessor configuration, the respective processors signal as they do for the PTLBE instruction to purge the entries of the address translation look-aside buffers of all processors.
The SSKE instruction designates a real address to modify a main storage key of the corresponding page. Since the real page address whose main storage key is to be modified and the corresponding main storage key may have already been stored in the address translation look-aside buffer, the main memory key of the entry corresponding to the real page address is updated when the SSKE instruction is issued. The SSKE instruction is also executed in synchronism among the processors of the multiprocessor as is done by the aforementioned instruction.
In a virtual machine system, when the above instruction is executed by a virtual machine (VM), a virtual machine control program (VMCP) which controls the virtual machine system grasps the event and simulates the instruction to execute the instruction.
When the virtual machine issues the IPTE instruction, the control program (VMCP) of the virtual machine system determines the contents of a page table entry based on the address translation table start address of the virtual machine, translates it to an absolute address of the virtual machine, further translates it to a real address of a real machine, and issues the IPTE instruction by utilizing a page table for the control program. When the control program issues the PTLBE instruction, the entire address translation look-aside buffer is purged. As a result, the entries of the address translation look-aside buffers related to the virtual machines other than the one which issued the IPTE instruction or the entries of the address translation look-aside buffers related to the control program are also invalidated. This may reduce performance of other virtual machines. In order to avoid it, the IPTE instruction is issued to invalidate the entry of the address look-aside translation buffer related to the virtual machine as much as possible.
The simulation by the VM control program (VMCP) of the IPTE instruction issued by an operating system (OS) on the VM has thus been described. Since an overhead of the VM is increased by this method, the IPTE instruction issued by the OS on the VM may be directly executed by hardware. Even in such a case, if the OS on the VM operates on only one of the processors of the system, the hardware cannot recognize it and it sends a signal to all processors of the multiprocessor system to request synchronous execution. Accordingly, the same problem as that described above takes place.
Where the virtual machine operates on a plurality of processors, it is possible for the virtual machine to occupy a specific processor for operation. In this case, if the IPTE instruction is issued by the virtual machine which occupies the processor, the address translation look-aside buffer related to the virtual machine is limited to the address translation look-aside buffer which belongs to the processor which has operated the virtual machine. However, in the prior art, when the entry of the address translation look-aside buffer is to be purged as a result of executing the IPTE instruction issued by the virtual machine, a signal is sent to other processors to unconditionally search corresponding entries in the address translation look-aside buffers of all the processors and to purge them if any. All processors execute the instruction synchronously and the next instruction is executed after the invalidation of the entries of the address translation look-aside buffers of all processors has been completed.
As described above, when the virtual machine operates on only one processor, the entry of the address translation look-aside buffer which the virtual machine may use is limited to the one belonging to that one processor but the signaling is effected to the entire system. As a result, excess purge of the entry of the address look-aside translation buffer due to the communication overhead among the processors and the execution of the IPTE instruction by other processors is possibly effected. This affects the efficiency of the overall system and lowers the system performance.